In modern CMOS technologies, embedded SiGe source/drain areas are standard in PFET devices as they improve performance by introducing uniaxial strain into the channel. Embedded SiGe integration occurs in early processes primarily for silicon-on-insulator (SOI) substrates and in late processes for bulk silicon substrates, with both HKMG gate first and last technologies. The integration of embedded SiGe, especially on the 28 nm technologies is performed early in the fabrication process, to maximize the amount of strain transferred into the channel and, therefore, improve performance.
HKMG gate last technologies generally use boron doped late SiGe, whereas HKMG gate first processes, especially for 32 nm and 28 nm technologies, form the gate first to obtain maximum performance of the device with an undoped non-sigma shaped cavity. With this type of integration, several problems occur. For example, encapsulation of the gate first HKMG and, therefore, yield issues arise, process complexity increases as additional steps are required, such as formation of sacrificial oxide spacers and differential disposable spacers, and removal of a dry nitride cap, which processes are costly.
A need therefore exists for methodology enabling fabrication of a low power high performance PMOS device with embedded SiGe source/drain regions and encapsulation of a gate first HKMG electrode, and the resulting device.